Four_step.Make
module Config : Core_config.S
val logcores : Base.int
module Gf = Gf.Signal
module Axi_stream : Hardcaml_axi.Stream.S
module Multi_parallel_cores : sig ... end
module I : sig ... end
module O : sig ... end
val create : build_mode:Hardcaml.Build_mode.t -> Hardcaml.Scope.t -> Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t
val hierarchy : build_mode:Hardcaml.Build_mode.t -> Hardcaml.Scope.t -> Hardcaml.Signal.t Hardcaml.Interface.Create_fn(I)(O).t