Module Dest.Of_signal

type comb = Hardcaml__.Signal.t
type t = comb t
val sexp_of_t : comb t -> Sexplib0.Sexp.t
val assert_widths : comb t -> Base.unit
val of_int : Base.int -> comb t
val const : Base.int -> comb t
val pack : ?rev:Base.bool -> comb t -> comb
val unpack : ?rev:Base.bool -> comb -> comb t
val mux : comb -> comb t Base.list -> comb t
val mux2 : comb -> comb t -> comb t -> comb t
val concat : comb t Base.list -> comb t
val priority_select : ( ( comb, comb t ) Hardcaml__.Comb.with_valid2 Base.list -> ( comb, comb t ) Hardcaml__.Comb.with_valid2 ) Hardcaml__.Comb.optional_branching_factor
val priority_select_with_default : ( ( comb, comb t ) Hardcaml__.Comb.with_valid2 Base.list -> default:comb t -> comb t ) Hardcaml__.Comb.optional_branching_factor
val onehot_select : ( ( comb, comb t ) Hardcaml__.Comb.with_valid2 Base.list -> comb t ) Hardcaml__.Comb.optional_branching_factor
val widths : t -> Base.int t
val of_ints : Base.int t -> t
val consts : Base.int t -> t
val wires : ?named:Base.bool -> ?from:t -> Base.unit -> t
val reg : ?enable:Hardcaml__.Signal.t -> Hardcaml__.Reg_spec.t -> t -> t
val pipeline : ?attributes:Hardcaml__.Rtl_attribute.t Base.list -> ?enable:Hardcaml__.Signal.t -> n:Base.int -> Hardcaml__.Reg_spec.t -> t -> t
val assign : t -> t -> Base.unit
val (<==) : t -> t -> Base.unit
val inputs : Base.unit -> t
val outputs : t -> t
val apply_names : ?prefix:Base.string -> ?suffix:Base.string -> ?naming_op:( Hardcaml__.Signal.t -> Base.string -> Hardcaml__.Signal.t ) -> t -> t
val validate : t -> Base.unit