Module `Field_ops_lib.Modulo_adder_pipe`

Computes (a + b mod P) over multiple pipeline stages.

This module requires a < P and b < P. Functionally, it implements the following over multiple pipeline stages.

mux2 ((a + b) >= P)
  ((a + b) - P)
  (a + b)

val latency : stages:int -> int

val hierarchical : 
  scope:Hardcaml.Scope.t ->
  clock:Hardcaml.Signal.t ->
  enable:Hardcaml.Signal.t ->
  stages:int ->
  p:Z.t ->
  Hardcaml.Signal.t ->
  Hardcaml.Signal.t ->
  Hardcaml.Signal.t

module With_interface (M : sig ... end) : sig ... end